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ee:hydrophones:start [2018/01/24 18:48] Ryan Summers |
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| ==== Software Design ==== | ==== Software Design ==== | ||
| + | The software design is straightforward, but the most complex of the other systems. Communication with other computers is implemented using UDP sockets provided by the lwIP (lightweight IP) library. When the CPU first boots, it loads the program off the SD card into memory. It then programs the FPGA bit stream and begins program execution after initializing most peripherals (e.g. Xilinx Ethernet). The application then initializes peripherals that were instantiated in the FPGA fabric (such as the ADC reader, the system monitor, and the SPI engine). It then configures the ADC chip and binds/connects to a variety of UDP ports for communication. | ||
| + | The software first attempts to sync onto the ping. Because the ping happens every two seconds, once the first ping has been found, the system can consistently find every other ping afterwards. To acquire initial synchronization, the code samples the hydrophones for 2.2 seconds. It then scans this period for the earliest start of a ping (by performing a threshold detection). It then calculates at what exact time the ping started and schedules sampling to begin at the next future ping. | ||
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| + | After sync is acquired, the software samples for approximately 250ms during the ping period. It then locates the ping and truncates around the start to minimize the amount of data that needs to be cross-correlated. The software marks the timestamp of the ping and schedules a time that the next ping should occur at. Finally, the data is then cross-correlated to calculate the time of arrivals for each ping. The software then transmits a variety of debug information (including all sample data, correlation calculations, and time of arrival deltas) over ethernet. The cycle continuously repeats until a ping is not detected in the 250ms sample period. If this occurs, it will try to regain sync by continuously sampling fro 2.2 seconds. | ||
| ===== Getting Started ===== | ===== Getting Started ===== | ||
| + | This section is designed to help a developer get started updating and programming the HydroZynq. | ||
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| === Code === | === Code === | ||
| + | All software and firmware is available in [[https://github.com/PalouseRobosub/hydro-zynq|the GitHub repository]]. There are two primary directories: hardware and software. The hardware folder contains all the Verilog and TCL files for interracting with Vivado. TCL scripts have been generated to rebuild the block design in vivado, and a README.txt file in proj/ describes how to use them. Additionally, the IO constraints file is provided for the current hardware. | ||
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| + | The software folder contains all C source code used in programming the HydroZynq. An ELF file can be created by using the `mk` script supplied with the source file name. All files located in src/ will be compiled against the application specified to generate the binary. Finally, a BOOT.bin file (binary image that is used for booting off the SD cared) can be created through the utilization of the 'doit' script. | ||
| + | Example: | ||
| + | ./doit app/main_bin.c bit/adc_dma_revb.bit | ||
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| + | This will automatically mount and copy over the BOOT.bin to the card for the HydroZynq. This script takes in the source file name of the main application as the first argument and the bit stream file as the second parameter. | ||
| + | The current firmware utilizes bit/adc_dma_revb.bit as the bitstream file. | ||
| === Programming === | === Programming === | ||
| === Communicating === | === Communicating === | ||
