Differences

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--- ee:hydrophones:start [2018/01/28 15:23]
Ryan Summers
+++ ee:hydrophones:start [2018/01/28 15:45]
Ryan Summers [System Design]
@@ Line 30: / Line 30: @@
 ==== Code ====
-All software and firmware is available in [[https://github.com/PalouseRobosub/hydro-zynq|the GitHub repository]]. There are two primary directories, ''%%hardware/%%'' and ''%%software/%%''. The ''%%hardware%%'' folder contains all the Verilog and TCL files for interacting with Vivado. TCL scripts have been generated to rebuild the block design in [[https://www.xilinx.com/products/design-tools/vivado.html|Vivado]], and a ''%%README.txt%%'' file in ''%%proj/%%'' describes how to use them. Additionally, the IO constraints file is provided for the current hardware.
+All software and firmware is available in [[https://github.com/PalouseRobosub/hydro-zynq|the GitHub repository]]. There are two primary directories, ''%%hardware/%%'' and ''%%software/%%''. The ''%%hardware/%%'' folder contains all the Verilog and TCL files for interacting with Vivado. TCL scripts have been generated to rebuild the block design in [[https://www.xilinx.com/products/design-tools/vivado.html|Vivado]], and a ''%%README.txt%%'' file in ''%%proj/%%'' describes how to use them. Additionally, the IO constraints file is provided for the current hardware.
-The software folder contains all C source code used in programming the HydroZynq. An ELF file can be created by using the `mk` script supplied with the source file name.
+The software folder contains all C source code used in programming the HydroZynq. An ELF file can be created by using the ''%%mk%%'' script supplied with the source file name.
 Example:
   ./mk app/main_bin.c
-All files located in src/ will be compiled against the application specified to generate the binary. Finally, a BOOT.bin file (binary image that is used for booting off the SD cared) can be created through the utilization of the 'doit' script.
+All files located in ''%%src/%%'' will be compiled against the application specified to generate the binary. Finally, a ''%%BOOT.bin%%'' file (binary image that is used for booting off the SD cared) can be created through the utilization of the ''%%doit%%'' script.
 Example:
   ./doit app/main_bin.c bit/adc_dma_revb.bit
-This will automatically mount and copy over the BOOT.bin to the card for the HydroZynq. This script takes in the source file name of the main application as the first argument and the bit stream file as the second parameter.
+This will automatically mount and copy over ''%%BOOT.bin%%'' to an SD card for the HydroZynq. This script takes in the source file name of the main application as the first argument and the bit stream file as the second parameter.
-**The current firmware utilizes software/bit/adc_dma_revb.bit as the bitstream file.**
+//The current firmware utilizes **software/bit/adc_dma_revb.bit** as the bitstream file.//
 ==== Programming & Debugging ====
-Programming and debugging can be completed through creation of new BOOT.bin files on the SD card, but this is often extremely inefficient. The [[https://store.digilentinc.com/jtag-hs3-programming-cable/|Digilent HS3]] can be used as a JTAG access point for GDB debug interfaces. To interact with the HydroZynq through JTAG, use the `xmd` command (provided by Xilinx).
+Programming and debugging can be completed through creation of a new ''%%BOOT.bin%%'' on the SD card, but this is often inefficient. The [[https://store.digilentinc.com/jtag-hs3-programming-cable/|Digilent HS3]] can be used as a JTAG access point for GDB debug interfaces. To interact with the HydroZynq through JTAG, use the ''%%xmd%%'' command (provided by the Xilinx Vivado tool suite).
 After executing xmd from the command line, you will enter a shell-like environment. To connect to the ARM core for programming, enter:
   > connect arm hw
-Once connected, if you desired to program the FPGA or the ARM, first stop the ARM CPU.
+Once connected, if you desired to program the FPGA or the ARM, stop the ARM CPU:
   > stop
-To program a new bitstream,
+To program a new bitstream:
   > fpga -f [bitstream_file_path]
-To load a new ELF onto the CPU,
+To load a new ELF onto the CPU:
   > dow [elf_file_path]
-Finally, the CPU can be restarted,
+Finally, the CPU can be restarted:
   > run
-Once XMD has been started, a remote GDB server is automatically instantiated. To connect to the GDB server, simply use the debug.sh script located in `software/` to launch up a GDB session.
+Once XMD has been started, a remote GDB server is automatically instantiated. To connect to the GDB server, use the ''%%software/debug.sh%%'' script to launch up a GDB session.
   [hydrozynq-repo-path]/software/debug.sh
 ==== Communication ====
-The HydroZynq communicates primarily through UDP. A number of user scripts have been created in the `scripts/` folder for ease of use with UDP. For example, the stdout of the application is sent to Cobalt's UDP port 3000 (e.g. 192.168.0.2:3000). A simple python application ([hydrozynq-repo-path]/scripts.debug_stream.py) can be used to view the standard output of the application (e.g. dbprintf() statements).
+The HydroZynq communicates through UDP. A number of user scripts have been created in the ''%%scripts/%%'' folder for ease of use with UDP. For example, the stdout of the application is sent to Cobalt's UDP port 3004 (e.g. 192.168.0.2:3004). A simple python application ([hydrozynq-repo-path]/scripts.debug_stream.py) can be used to view the standard output of the application (such as dbprintf() statements).
 === Port Descriptions ===
@@ Line 79: / Line 79: @@
 | 3004        | Cobalt      | Debug/STDOUT port                 |
-Note that the HydroZynq does not run ROS natively, so python scripts running on cobalt are necessary for interfacing the HydroZynq with ROS. As of now, these scripts are still under initial development.
+Note that the HydroZynq does not run ROS natively, so python scripts running on cobalt are necessary for interfacing the HydroZynq with ROS. As of now, these scripts are still under development.
-The HydroZynq currently sends out all data used in the cross-correlation and the results of the final cross-correlation. These can be visualized using python and MatPlotLib through the scripts made available:
+The HydroZynq currently sends out all samples used in the cross correlation and the results of the final cross-correlation. These can be visualized using python and MatPlotLib through the scripts made available here:
   python [hydrozynq-repo-path]/scripts/data_receiver.py
@@ Line 87: / Line 87: @@
 The data and correlation results are sent using a trivial packet format:
-<packet_number as unsigned, little-endian 4-byte integer> <Sample 1> ... <Sample N>
+{{ :ee:hydrophones:wavedrom.png |Packet Formats}}
-Data results contain 4 channels per Sample, where each channel is a 16-bit unsigned integer (little-endian) value. (E.g. each sample is 64 bits and has 4 values).
+All data is little-endian integers. Bit sizes are shown in parentheses. Data packets send the raw ADC reading for each point and correlation packets send the correlation function values for each time shift calculated.
-Correlation results contain 3 channels per Sample, where each channel is a 4-byte integer (little-endian) value. The first sample is the correlation between Channel 1 and reference, teh second is between Channel 2 and reference, and the last is between Channel 3 and reference.
+The HydroZynq also allows for run-time parameters to be set dynamically, including the ping detection threshold. These can be sent to the HydroZynq command port in a simple ASCII string.
-The HydroZynq allows for a number of run-time parameters to be set dynamically, including the ping detection threshold. These can be sent to the HydroZynq command port in a simple ASCII string.
   [keyword]:[value],[keyword]:[value],.... (etc)
-Note that the string must terminate without a trailing comma and that it is able to only have a single key-value pair. The current supported keys are as follows:
+Examples:
+  threshold:500,debug:1
+  reset:1
+The supported keys are as follows:
 ^ Key String ^ Data Type ^ Description ^
 | reset      | N/A          | Causes the Zynq to perform a software reset. |
@@ Line 102: / Line 105: @@
 | debug      | unsigned int | If data is 0, HydroZynq debug mode is disabled. Otherwise, debug mode is enabled. |
-In debug mode, the HydroZynq records for 2.1 seconds, dumps data to the data stream port, and repeats. No correlations are performed.
+In debug mode, the HydroZynq records for 2.1 seconds, dumps all 2.1 seconds of data to the data stream port, and repeats. No correlations are performed and no result is sent.
 ===== Hardware =====
@@ Line 117: / Line 120: @@
 {{ :ee:hydrophones:hydrophones-system-architecture.jpg}}
-The hydrophones have small piezo sensors that output very small voltages as sound hits them. To be able to read them, the hydrophone signals are filtered with a 1st order bandpass and then are gained by approximately 40-60dB. After the signals are amplified, they are then passed to the ADC for conversion. The ADC samples the hydrophone signals at 5MHz simultaneously and outputs the converted information over a custom, parallel interface. This interface is differential and utilizes DDR. In order to read the ADC values, the Zynq SoC (System on a Chip) is used. The Zynq has a dual core ARM processor embedded in FPGA fabric. A custom Verilog module was created for reading the parallel interface output by the ADC. The data is then sent over the AXI4-Stream protocol to allow it to be transferred into the processor's RAM through the HP-AXI interface (AXI is a common communication protocol for custom hardware modules written in Verilog). In order to accomodate the high data rate of the analog measurements, the AXI stream is connected to a DMA engine. At this point, the data has been successfully transferred into the computer and the cross correlation can be performed. The below sections delve into specifics of each of the different design areas.
+The hydrophones have a piezo sensors that outputs small voltages as sound hits them. To be able to read them, the hydrophone signals are filtered with a 1st order bandpass and then are gained by approximately 40-60dB. After the signals are amplified, they are then passed to the ADC for conversion. The ADC samples the hydrophone signals at 5MHz simultaneously and outputs the converted information over a custom, parallel interface. This interface is differential and utilizes DDR. In order to read the ADC values, the Zynq SoC is used. The Zynq has a dual core ARM processor embedded in FPGA fabric. A custom Verilog module was created for reading the parallel interface output by the ADC. The data is then sent over the AXI4-Stream protocol to allow it to be transferred into the processor's RAM through the HP-AXI interface (AXI is a common communication protocol for custom hardware modules written in Verilog). In order to accommodate the high data rate of the analog measurements, the AXI stream is connected to a DMA engine. The DMA puts the data into the CPU RAM and tells the processor about it. At this point, the data has been successfully transferred into the computer and the cross correlation can be performed. The below sections delve into specifics of each of the different design areas.
 ==== Analog Design ====

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