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ee:hydrophones:start [2018/01/28 15:41] Ryan Summers |
ee:hydrophones:start [2018/01/28 15:45] Ryan Summers [System Design] |
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| reset:1 | reset:1 | ||
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| - | Note that the string must terminate without a trailing comma and that it is able to only have a single key-value pair. The current supported keys are as follows: | + | The supported keys are as follows: |
| ^ Key String ^ Data Type ^ Description ^ | ^ Key String ^ Data Type ^ Description ^ | ||
| | reset | N/A | Causes the Zynq to perform a software reset. | | | reset | N/A | Causes the Zynq to perform a software reset. | | ||
| Line 105: | Line 105: | ||
| | debug | unsigned int | If data is 0, HydroZynq debug mode is disabled. Otherwise, debug mode is enabled. | | | debug | unsigned int | If data is 0, HydroZynq debug mode is disabled. Otherwise, debug mode is enabled. | | ||
| - | In debug mode, the HydroZynq records for 2.1 seconds, dumps data to the data stream port, and repeats. No correlations are performed. | + | In debug mode, the HydroZynq records for 2.1 seconds, dumps all 2.1 seconds of data to the data stream port, and repeats. No correlations are performed and no result is sent. |
| ===== Hardware ===== | ===== Hardware ===== | ||
| Line 120: | Line 120: | ||
| {{ :ee:hydrophones:hydrophones-system-architecture.jpg}} | {{ :ee:hydrophones:hydrophones-system-architecture.jpg}} | ||
| - | The hydrophones have small piezo sensors that output very small voltages as sound hits them. To be able to read them, the hydrophone signals are filtered with a 1st order bandpass and then are gained by approximately 40-60dB. After the signals are amplified, they are then passed to the ADC for conversion. The ADC samples the hydrophone signals at 5MHz simultaneously and outputs the converted information over a custom, parallel interface. This interface is differential and utilizes DDR. In order to read the ADC values, the Zynq SoC (System on a Chip) is used. The Zynq has a dual core ARM processor embedded in FPGA fabric. A custom Verilog module was created for reading the parallel interface output by the ADC. The data is then sent over the AXI4-Stream protocol to allow it to be transferred into the processor's RAM through the HP-AXI interface (AXI is a common communication protocol for custom hardware modules written in Verilog). In order to accomodate the high data rate of the analog measurements, the AXI stream is connected to a DMA engine. At this point, the data has been successfully transferred into the computer and the cross correlation can be performed. The below sections delve into specifics of each of the different design areas. | + | The hydrophones have a piezo sensors that outputs small voltages as sound hits them. To be able to read them, the hydrophone signals are filtered with a 1st order bandpass and then are gained by approximately 40-60dB. After the signals are amplified, they are then passed to the ADC for conversion. The ADC samples the hydrophone signals at 5MHz simultaneously and outputs the converted information over a custom, parallel interface. This interface is differential and utilizes DDR. In order to read the ADC values, the Zynq SoC is used. The Zynq has a dual core ARM processor embedded in FPGA fabric. A custom Verilog module was created for reading the parallel interface output by the ADC. The data is then sent over the AXI4-Stream protocol to allow it to be transferred into the processor's RAM through the HP-AXI interface (AXI is a common communication protocol for custom hardware modules written in Verilog). In order to accommodate the high data rate of the analog measurements, the AXI stream is connected to a DMA engine. The DMA puts the data into the CPU RAM and tells the processor about it. At this point, the data has been successfully transferred into the computer and the cross correlation can be performed. The below sections delve into specifics of each of the different design areas. |
| ==== Analog Design ==== | ==== Analog Design ==== | ||
