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ee:hydrophones:start [2018/01/28 15:46] Ryan Summers [Software Design] |
ee:hydrophones:start [2018/01/28 15:46] Ryan Summers [Software Design] |
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| ==== Software Design ==== | ==== Software Design ==== | ||
| - | //Note that for ease of use, the HydroZynq is programmed bare-metal. There is no operating system on the board!// | + | //Note: For simplicity, the HydroZynq is programmed bare-metal. There is no operating system on the board!// |
| The software design is straightforward, but the most complex of the other systems. Communication with other computers is implemented using UDP sockets provided by the lwIP (lightweight IP) library. When the CPU first boots, it loads the program off the SD card into memory. It then programs the FPGA bit stream and begins program execution after initializing most peripherals (e.g. Xilinx Ethernet). The application then initializes peripherals that were instantiated in the FPGA fabric (such as the ADC reader, the system monitor, and the SPI engine). It then configures the ADC chip and binds/connects to a variety of UDP ports for communication. | The software design is straightforward, but the most complex of the other systems. Communication with other computers is implemented using UDP sockets provided by the lwIP (lightweight IP) library. When the CPU first boots, it loads the program off the SD card into memory. It then programs the FPGA bit stream and begins program execution after initializing most peripherals (e.g. Xilinx Ethernet). The application then initializes peripherals that were instantiated in the FPGA fabric (such as the ADC reader, the system monitor, and the SPI engine). It then configures the ADC chip and binds/connects to a variety of UDP ports for communication. | ||
