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ee:hydrophones:start [2018/01/28 15:56] Ryan Summers [Analog Design] |
ee:hydrophones:start [2018/03/20 04:53] Ryan Summers [Communication] |
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The analog signal goes through a five-stage amplification and filtering process. First, the signal is sent through two gain stages, each of which apply an adjustable gain to the signal. After the signal is gained into a reasonable voltage range, it is passed through a low-pass filter and then a high-pass filter to result in a bandpass filter of the signal. | The analog signal goes through a five-stage amplification and filtering process. First, the signal is sent through two gain stages, each of which apply an adjustable gain to the signal. After the signal is gained into a reasonable voltage range, it is passed through a low-pass filter and then a high-pass filter to result in a bandpass filter of the signal. | ||
- | Once the signal has been filtered and gained, it is preprocessed for the ADC. In order to acquire more accurate measurements, the ADC requires signals to be differential. The analog signals are therefore put through a signle-ended to differential converter. Immediately before the signals enter the ADC, there is a low-pass anti-aliasing filtering. This filter guarantees Niquist criteria, which means that any frequencies detected in the sampled signal will not be aliases of higher frequencies. | + | Once the signal has been filtered and gained, it is preprocessed for the ADC. In order to acquire more accurate measurements, the ADC requires signals to be [[https://en.wikipedia.org/wiki/Differential_signaling|differential]]. The analog signals are therefore put through a single-ended to [[https://en.wikipedia.org/wiki/Differential_signaling|differential]] converter and biased around a DC voltage supplied by the ADC. Immediately before the signals enter the ADC, there is a low-pass anti-aliasing filtering (Low-pass differential RC). |
==== FPGA Design ==== | ==== FPGA Design ==== | ||
- | The FPGA has a number of parts to it, but its ultimate goal is to take samples sent from the ADC and transfer them into the processor's memory. Immediately, the differential signals are passed to the FPGA IO buffers to convert them to single-ended. After the single-ended conversion, a custom Verilog block was written that takes in the ADC's clock and data signals to properly digitize the data. It then provides this data on an AXI-Stream interface. Because ADC reader block is driven off an external clock and the rest of the FPGA is clocked internally, care must be taken to cross the clock boundaries to prevent metastability. The Xilinx FIFO generator was used, as it generates an asynchronous read-write FIFO that can be used for synchronizing data with the internal FPGA clock. | + | {{ :ee:hydrophones:fpga-hydrozynq.jpg |}} |
+ | |||
+ | The FPGA has a number of parts to it, but its ultimate goal is to take samples sent from the ADC and transfer them into the processor's memory. Immediately, the [[https://en.wikipedia.org/wiki/Differential_signaling|differential signals]] are passed to the FPGA IO buffers to convert them to single-ended. After the single-ended conversion, a custom Verilog block was written that takes in the ADC's clock and data signals to properly digitize the data. It then provides this data on an [[https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf|AXI-Stream]] interface. Because ADC reader block is driven off an external clock and the rest of the FPGA is clocked internally, care must be taken to cross the clock boundaries to prevent metastability. The Xilinx FIFO generator was used, as it generates an asynchronous read-write FIFO that can be used for synchronizing data with the internal FPGA clock. | ||
After synchronization, the AXI stream is connected to a Stream-To-Multi-Master Direct Memory Access (S2MM DMA) engine. The DMA engine is a software-programmable peripheral that will asynchronously write the ADC samples into the processor's RAM. | After synchronization, the AXI stream is connected to a Stream-To-Multi-Master Direct Memory Access (S2MM DMA) engine. The DMA engine is a software-programmable peripheral that will asynchronously write the ADC samples into the processor's RAM. | ||
- | There are a few other features implemented in the FPGA fabric, including the XSystemMonitor, which monitors the FPGA temperature. There is also a SPI module implemented that is used to program the ADC internal registers and verify its functionality. In Rev C of the HydroZynq, the manually adjustable potentiometers have been replaced with SPI-programmable potentiometers, which allows the analog gain of the signal to be controlled digitally. | + | There are a few other features implemented in the FPGA fabric, including the XSystemMonitor, which monitors the FPGA temperature, and a SPI module implemented that is used to program the ADC internal registers and verify its functionality. In Rev C of the HydroZynq, the manually adjustable potentiometers have been replaced with SPI-programmable potentiometers, which allows the analog gain of the signal to be controlled digitally. |
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//Note: For simplicity, the HydroZynq is programmed bare-metal. There is no operating system on the board!// | //Note: For simplicity, the HydroZynq is programmed bare-metal. There is no operating system on the board!// | ||
- | The software design is straightforward, but the most complex of the other systems. Communication with other computers is implemented using UDP sockets provided by the lwIP (lightweight IP) library. When the CPU first boots, it loads the program off the SD card into memory. It then programs the FPGA bit stream and begins program execution after initializing most peripherals (e.g. Xilinx Ethernet). The application then initializes peripherals that were instantiated in the FPGA fabric (such as the ADC reader, the system monitor, and the SPI engine). It then configures the ADC chip and binds/connects to a variety of UDP ports for communication. | + | The software design is straightforward, but the most complex of the other systems. Communication with other computers is implemented using UDP sockets provided by the [[http://www.nongnu.org/lwip/2_0_x/index.html|lwIP (lightweight IP) library]]. When the CPU first boots, it loads the program off the SD card into memory. It then programs the FPGA bit stream and begins program execution after initializing most of the hardware peripherals, such as the Xilinx Gigabit-Ethernet peripheral. The application is then responsible for initializing soft peripherals that were instantiated in the FPGA fabric (such as the ADC reader, the system monitor, and the SPI engine). It configures the ADC chip and binds/connects to a variety of UDP ports for communication. |
- | The software first attempts to sync onto the ping. Because the ping happens every two seconds, once the first ping has been found, the system can consistently find every other ping afterwards. To acquire initial synchronization, the code samples the hydrophones for 2.2 seconds. It then scans this period for the earliest start of a ping (by performing a threshold detection). It then calculates at what exact time the ping started and schedules sampling to begin at the next future ping. | + | The software first attempts to sync onto the ping. Because the ping happens every two seconds, once the first ping has been found, the system can consistently find every other ping afterwards. To acquire initial synchronization, the code samples the hydrophones for 2.1 seconds and scans the data for the earliest start of a ping (by performing a threshold detection). Then, it calculates at what exact time the ping started and schedules sampling to begin at the next ping. |
- | After sync is acquired, the software samples for approximately 250ms during the ping period. It then locates the ping and truncates around the start to minimize the amount of data that needs to be cross-correlated. The software marks the timestamp of the ping and schedules a time that the next ping should occur at. Finally, the data is then cross-correlated to calculate the time of arrivals for each ping. The software then transmits a variety of debug information (including all sample data, correlation calculations, and time of arrival deltas) over ethernet. The cycle continuously repeats until a ping is not detected in the 250ms sample period. If this occurs, it will try to regain sync by continuously sampling fro 2.2 seconds. | + | After sync is acquired, the software samples for approximately 250ms during the ping period. It then verifies that the ping is present and truncates around the start of the ping to minimize the amount of data that needs to be cross-correlated. The software marks the timestamp of the ping and schedules a time that the next ping should occur at. Finally, the data is then cross-correlated to calculate the time of arrival delays for each ping. The software then transmits a variety of debug information (including all sample data, correlation calculations, and time of arrival deltas) over ethernet. The cycle continuously repeats until a ping is not detected in the 250ms sample period. If this occurs, the application will try to regain sync by continuously sampling for 2.1 seconds. |
===== Getting Started ===== | ===== Getting Started ===== | ||
This section is designed to help a developer get started updating and programming the HydroZynq. | This section is designed to help a developer get started updating and programming the HydroZynq. | ||
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//The current firmware utilizes **software/bit/adc_dma_revb.bit** as the bitstream file.// | //The current firmware utilizes **software/bit/adc_dma_revb.bit** as the bitstream file.// | ||
+ | |||
+ | ==== Cross-Compile FFTW3 ==== | ||
+ | In order to perform frequency analysis, the HydroZynq utilizes the FFTW3 libraries. In order to generate the libfftw3.a library and the associated header files, it is necessary to compile FFTW from scratch. This can be completed by downloading the FFTW tarball from [[http://www.fftw.org/download.html|here]]. Next, untar the tarball, create an output directory for the library and headers, and configure FFTW before installation with the following options: | ||
+ | mkdir build | ||
+ | ./configure --host=arm-none-eabi "CFLAGS=--specs=nosys.specs -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" --enable-armv7a-cntvct --prefix=`pwd`/build | ||
+ | make -j4 | ||
+ | make install | ||
+ | |||
+ | The library and appropriate headers will now be in the ''%%build/%%'' directory. | ||
==== Programming & Debugging ==== | ==== Programming & Debugging ==== | ||
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=== Port Descriptions === | === Port Descriptions === | ||
^ Port Number ^ Destination ^ Description ^ | ^ Port Number ^ Destination ^ Description ^ | ||
- | | 3000 | HydroZynq | Command port | | + | | 3000 | HydroZynq | Command port | |
- | | 3001 | Cobalt | Sample data stream port | | + | | 3001 | Cobalt | Sample data stream port | |
- | | 3002 | Cobalt | Time of Arrival Delay result port | | + | | 3002 | Cobalt | Time of Arrival Delay result port | |
- | | 3003 | Cobalt | Cross-correlation stream port | | + | | 3003 | Cobalt | Cross-correlation stream port | |
- | | 3004 | Cobalt | Debug/STDOUT port | | + | | 3004 | Cobalt | Debug/STDOUT port | |
+ | | 3005 | Cobalt | Requests to silence the control system. | | ||
Note that the HydroZynq does not run ROS natively, so python scripts running on cobalt are necessary for interfacing the HydroZynq with ROS. As of now, these scripts are still under development. | Note that the HydroZynq does not run ROS natively, so python scripts running on cobalt are necessary for interfacing the HydroZynq with ROS. As of now, these scripts are still under development. | ||
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| threshold | unsigned int | Sets the HydroZynq ping ADC threshold value. | | | threshold | unsigned int | Sets the HydroZynq ping ADC threshold value. | | ||
| debug | unsigned int | If data is 0, HydroZynq debug mode is disabled. Otherwise, debug mode is enabled. | | | debug | unsigned int | If data is 0, HydroZynq debug mode is disabled. Otherwise, debug mode is enabled. | | ||
+ | | frequency | unsigned int | Specifies target pinger frequency. May be 25000, 30000, 35000, or 40000. Units are Hz. | | ||
+ | | post_ping_duration_us | unsigned int | The number of microseconds after ping threshold to truncate the signal to. //Default: 50 us// | ||
+ | | pre_ping_duration_us | unsigned int | The number of microseconds before ping threshold to truncate the signal to. //Default: 100 us//| | ||
+ | | filter | unsigned int | If data is 0, IIR filtering is disabled. Otherwise, filter is enabled. //Default: disabled.// | | ||
In debug mode, the HydroZynq records for 2.1 seconds, dumps all 2.1 seconds of data to the data stream port, and repeats. No correlations are performed and no result is sent. | In debug mode, the HydroZynq records for 2.1 seconds, dumps all 2.1 seconds of data to the data stream port, and repeats. No correlations are performed and no result is sent. |