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ee:hydrophones:start [2018/01/28 16:36] Ryan Summers [Software Design] |
ee:hydrophones:start [2020/03/06 01:20] (current) Chris Nathman [Communication] |
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| The analog signal goes through a five-stage amplification and filtering process. First, the signal is sent through two gain stages, each of which apply an adjustable gain to the signal. After the signal is gained into a reasonable voltage range, it is passed through a low-pass filter and then a high-pass filter to result in a bandpass filter of the signal. | The analog signal goes through a five-stage amplification and filtering process. First, the signal is sent through two gain stages, each of which apply an adjustable gain to the signal. After the signal is gained into a reasonable voltage range, it is passed through a low-pass filter and then a high-pass filter to result in a bandpass filter of the signal. | ||
| - | Once the signal has been filtered and gained, it is preprocessed for the ADC. In order to acquire more accurate measurements, the ADC requires signals to be differential. The analog signals are therefore put through a single-ended to differential converter and biased around a DC voltage supplied by the ADC. Immediately before the signals enter the ADC, there is a low-pass anti-aliasing filtering (Low-pass differential RC). | + | Once the signal has been filtered and gained, it is preprocessed for the ADC. In order to acquire more accurate measurements, the ADC requires signals to be [[https://en.wikipedia.org/wiki/Differential_signaling|differential]]. The analog signals are therefore put through a single-ended to [[https://en.wikipedia.org/wiki/Differential_signaling|differential]] converter and biased around a DC voltage supplied by the ADC. Immediately before the signals enter the ADC, there is a low-pass anti-aliasing filtering (Low-pass differential RC). |
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| {{ :ee:hydrophones:fpga-hydrozynq.jpg |}} | {{ :ee:hydrophones:fpga-hydrozynq.jpg |}} | ||
| - | The FPGA has a number of parts to it, but its ultimate goal is to take samples sent from the ADC and transfer them into the processor's memory. Immediately, the differential signals are passed to the FPGA IO buffers to convert them to single-ended. After the single-ended conversion, a custom Verilog block was written that takes in the ADC's clock and data signals to properly digitize the data. It then provides this data on an [[https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf|AXI-Stream]] interface. Because ADC reader block is driven off an external clock and the rest of the FPGA is clocked internally, care must be taken to cross the clock boundaries to prevent metastability. The Xilinx FIFO generator was used, as it generates an asynchronous read-write FIFO that can be used for synchronizing data with the internal FPGA clock. | + | The FPGA has a number of parts to it, but its ultimate goal is to take samples sent from the ADC and transfer them into the processor's memory. Immediately, the [[https://en.wikipedia.org/wiki/Differential_signaling|differential signals]] are passed to the FPGA IO buffers to convert them to single-ended. After the single-ended conversion, a custom Verilog block was written that takes in the ADC's clock and data signals to properly digitize the data. It then provides this data on an [[https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf|AXI-Stream]] interface. Because ADC reader block is driven off an external clock and the rest of the FPGA is clocked internally, care must be taken to cross the clock boundaries to prevent metastability. The Xilinx FIFO generator was used, as it generates an asynchronous read-write FIFO that can be used for synchronizing data with the internal FPGA clock. |
| After synchronization, the AXI stream is connected to a Stream-To-Multi-Master Direct Memory Access (S2MM DMA) engine. The DMA engine is a software-programmable peripheral that will asynchronously write the ADC samples into the processor's RAM. | After synchronization, the AXI stream is connected to a Stream-To-Multi-Master Direct Memory Access (S2MM DMA) engine. The DMA engine is a software-programmable peripheral that will asynchronously write the ADC samples into the processor's RAM. | ||
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| ==== Code ==== | ==== Code ==== | ||
| - | All software and firmware is available in [[https://github.com/PalouseRobosub/hydro-zynq|the GitHub repository]]. There are two primary directories, ''%%hardware/%%'' and ''%%software/%%''. The ''%%hardware/%%'' folder contains all the Verilog and TCL files for interacting with Vivado. TCL scripts have been generated to rebuild the block design in [[https://www.xilinx.com/products/design-tools/vivado.html|Vivado]], and a ''%%README.txt%%'' file in ''%%proj/%%'' describes how to use them. Additionally, the IO constraints file is provided for the current hardware. | + | All software and firmware is available in [[https://gitlab.com/PalouseRobosub/Electrical/hydro-zynq|the Gitlab repository]]. There are two primary directories, ''%%hardware/%%'' and ''%%software/%%''. The ''%%hardware/%%'' folder contains all the Verilog and TCL files for interacting with Vivado. TCL scripts have been generated to rebuild the block design in [[https://www.xilinx.com/products/design-tools/vivado.html|Vivado]], and a ''%%README.txt%%'' file in ''%%proj/%%'' describes how to use them. Additionally, the IO constraints file is provided for the current hardware. |
| The software folder contains all C source code used in programming the HydroZynq. An ELF file can be created by using the ''%%mk%%'' script supplied with the source file name. | The software folder contains all C source code used in programming the HydroZynq. An ELF file can be created by using the ''%%mk%%'' script supplied with the source file name. | ||
| Line 71: | Line 71: | ||
| ./mk app/main_bin.c | ./mk app/main_bin.c | ||
| - | All files located in ''%%src/%%'' will be compiled against the application specified to generate the binary. Finally, a ''%%BOOT.bin%%'' file (binary image that is used for booting off the SD cared) can be created through the utilization of the ''%%doit%%'' script. | + | All files located in ''%%src/%%'' will be compiled against the application specified to generate the binary. |
| + | |||
| + | ==== Programming & Debugging ==== | ||
| + | In order to generate a boot-able ''%%BOOT.bin%%'' file (binary image that is used for booting off the SD card), utilize the ''%%doit%%'' script in the ''%%software/%%'' directory. | ||
| Example: | Example: | ||
| Line 79: | Line 82: | ||
| //The current firmware utilizes **software/bit/adc_dma_revb.bit** as the bitstream file.// | //The current firmware utilizes **software/bit/adc_dma_revb.bit** as the bitstream file.// | ||
| - | + | In order to efficiently debug through GDB and program on the fly, the [[https://store.digilentinc.com/jtag-hs3-programming-cable/|Digilent HS3]] can be used as a JTAG access point for GDB debug interfaces. To interact with the HydroZynq through JTAG, use the ''%%xmd%%'' command (provided by the Xilinx Vivado tool suite). | |
| - | ==== Programming & Debugging ==== | + | |
| - | Programming and debugging can be completed through creation of a new ''%%BOOT.bin%%'' on the SD card, but this is often inefficient. The [[https://store.digilentinc.com/jtag-hs3-programming-cable/|Digilent HS3]] can be used as a JTAG access point for GDB debug interfaces. To interact with the HydroZynq through JTAG, use the ''%%xmd%%'' command (provided by the Xilinx Vivado tool suite). | + | |
| After executing xmd from the command line, you will enter a shell-like environment. To connect to the ARM core for programming, enter: | After executing xmd from the command line, you will enter a shell-like environment. To connect to the ARM core for programming, enter: | ||
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| === Port Descriptions === | === Port Descriptions === | ||
| ^ Port Number ^ Destination ^ Description ^ | ^ Port Number ^ Destination ^ Description ^ | ||
| - | | 3000 | HydroZynq | Command port | | + | | 3000 | HydroZynq | Command port | |
| - | | 3001 | Cobalt | Sample data stream port | | + | | 3001 | Cobalt | Sample data stream port | |
| - | | 3002 | Cobalt | Time of Arrival Delay result port | | + | | 3002 | Cobalt | Time of Arrival Delay result port | |
| - | | 3003 | Cobalt | Cross-correlation stream port | | + | | 3003 | Cobalt | Cross-correlation stream port | |
| - | | 3004 | Cobalt | Debug/STDOUT port | | + | | 3004 | Cobalt | Debug/STDOUT port | |
| + | | 3005 | Cobalt | Requests to silence the control system. | | ||
| Note that the HydroZynq does not run ROS natively, so python scripts running on cobalt are necessary for interfacing the HydroZynq with ROS. As of now, these scripts are still under development. | Note that the HydroZynq does not run ROS natively, so python scripts running on cobalt are necessary for interfacing the HydroZynq with ROS. As of now, these scripts are still under development. | ||
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| reset:1 | reset:1 | ||
| + | |||
| + | frequency 35000 | ||
| | | ||
| The supported keys are as follows: | The supported keys are as follows: | ||
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| | threshold | unsigned int | Sets the HydroZynq ping ADC threshold value. | | | threshold | unsigned int | Sets the HydroZynq ping ADC threshold value. | | ||
| | debug | unsigned int | If data is 0, HydroZynq debug mode is disabled. Otherwise, debug mode is enabled. | | | debug | unsigned int | If data is 0, HydroZynq debug mode is disabled. Otherwise, debug mode is enabled. | | ||
| + | | frequency | unsigned int | Specifies target pinger frequency. May be 25000, 30000, 35000, or 40000. Units are Hz. **This must be set or the zynq will not look for pings.** | | ||
| + | | post_ping_duration_us | unsigned int | The number of microseconds after ping threshold to truncate the signal to. //Default: 50 us//| | ||
| + | | pre_ping_duration_us | unsigned int | The number of microseconds before ping threshold to truncate the signal to. //Default: 100 us//| | ||
| + | | filter | unsigned int | If data is 0, IIR filtering is disabled. Otherwise, filter is enabled. //Default: disabled.// | | ||
| + | | min_fft_samples | unsigned int | The minimum number of samples to be used in Fourier transforms. In situations where fewer than this number of samples are available (e.g. ping detected close to end of sample set such that only a small number of samples are left before the end of the data array), a fourier transform will not be performed and the zynq will have to resync with the ping. Performing Fourier transforms on small numbers of samples will likely cause inaccurate frequencies to be reported. //Default: 2048// | | ||
| + | | print | N/A | Prints out all current zynq parameter values. | | ||
| In debug mode, the HydroZynq records for 2.1 seconds, dumps all 2.1 seconds of data to the data stream port, and repeats. No correlations are performed and no result is sent. | In debug mode, the HydroZynq records for 2.1 seconds, dumps all 2.1 seconds of data to the data stream port, and repeats. No correlations are performed and no result is sent. | ||
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| | Analog-to-Digital Converter | LTC2171-14 | [[http://cds.linear.com/docs/en/datasheet/21721014fb.pdf|Datasheet]]| | | Analog-to-Digital Converter | LTC2171-14 | [[http://cds.linear.com/docs/en/datasheet/21721014fb.pdf|Datasheet]]| | ||
| + | === Hydrophone dimensions: === | ||
| + | {{:ee:hydrophones:as-1_hydrophone_dimensions.jpg}} | ||
